IBM Statement of Non-Assertion
of Named Patents Against OSS
IBM is committed to
promoting innovation for the benefit of our customers and for the overall
growth and advancement of the information technology field. IBM takes many actions
to promote innovation. Today, we are announcing a new innovation initiative. We
are pledging the free use of 500 of our U.S. patents, as well as all
counterparts of these patents issued in other countries, in the development,
distribution, and use of open source software. We believe that the open source
community has been at the forefront of innovation and we are taking this action
to encourage additional innovation for open platforms. The following is the
text of our pledge. It is our intent that this pledge be legally binding and
enforceable by any open source software developer, distributor, or user who
uses one or more of the 500 listed U.S. patents and/or the counterparts of
these patents issued in other countries.
IBM's Legally Binding
Commitment Not To Assert the 500 Named Patents Against OSS
The pledge will benefit
any Open Source Software. Open Source Software is any computer software program
whose source code is published and available for inspection and use by anyone,
and is made available under a license agreement that permits recipients to
copy, modify and distribute the program’s source code without payment of fees
or royalties. All licenses certified by opensource.org and listed on their
website as of 01/11/2005 are Open Source Software licenses for the purpose of
this pledge..
IBM hereby commits not
to assert any of the 500 U.S. patents listed below, as well as all counterparts
of these patents issued in other countries, against the development, use or
distribution of Open Source Software.
In order to foster
innovation and avoid the possibility that a party will take advantage of this
pledge and then assert patents or other intellectual property rights of its own
against Open Source Software, thereby limiting the freedom of IBM or any other
Open Source Software developer to create innovative software programs, the
commitment not to assert any of these 500 U.S. patents and all counterparts of
these patents issued in other countries is irrevocable except that IBM reserves
the right to terminate this patent pledge and commitment only with regard to
any party who files a lawsuit asserting patents or other intellectual property
rights against Open Source Software.
Background information
on 500 pledged patents
Publication Title
US6317811
Method and system for reissuing load requests in a multi-stream prefetch design
US6298435
Methods and apparatus for exploiting virtual buffers to increase instruction
parallelism in a pipelined processor
US6298417
Pipelined cache memory deallocation and storeback
US6286094
Method and system for optimizing the fetching of dispatch groups in a
superscalar processor
US6279105
Pipelined two-cycle branch target address cache
US6266767
Apparatus and method for facilitating out-of-order execution of load
instructions
US6240474
Pipelined read transfers
US6237081
Queuing method and apparatus for facilitating the rejection of sequential
instructions in a processor
US6219743
Apparatus for dynamic resource mapping for isolating interrupt sources and
method therefore
US6202128
Method and system for pre-fetch cache interrogation using snoop port
US6189065
Method and apparatus for interrupt load balancing for powerPC processors
US5659722
Multiple condition code branching system in a multi-processor environment
US5655141
Method and system for storing information in a processing system
US5644779
Processing system and method of operation for concurrent processing of branch
instructions with canceling of processing of a branch instruction
US5619408
Method and system for recoding
noneffective instructions within a data processing system
US5615360
Method for interfacing
applications with a content addressable memory
US5253349
Decreasing processing time for
type 1 dyadic instructions
US5224215
Message queue processing among
cooperative processors having significant speed differences
Publication Title
US6237067
System and method for handling
storage consistency conflict
US6230219
High performance multichannel
DMA controller for a PCI host bridge with a built-in cache
US6219737
Read request performance of a
multiple set buffer pool bus bridge
US5671370
Alternating data valid control
signals for high performance data transfer
US5659696
Method and apparatus for
determining address location and taking one of two actions depending on the
type of read/write data transfer required
US5634007
Independent computer storage
addressing in input/output transfers
US5613163
Method and system for
predefined suspension and resumption control over I/O programs
US5224213
Ping-pong data buffer for
transferring data from one data bus to another data bus
US5195185
Dynamic bus arbitration with
concurrent same bus granting every cycle
Publication Title
US6334172
Cache coherency protocol with
tagged state for modified values
US6311253
Methods for caching cache tags
US6304939
Token mechanism for cache-line
replacement within a cache memory having redundant cache lines
US6275908
Cache coherency protocol
including an HR state
US6272603
Cache coherency protocol
having hovering (H), recent (R), and tagged (T) states
US6272601
Critical word forwarding in a
multiprocessor system
US6263407
Cache coherency protocol
including a hovering (H) state having a precise mode and an imprecise mode
US6240489
Method for implementing a
pseudo least recent used (LRU) mechanism in a four-way cache memory within a
data processing system
US6226725
Method and system in a data
processing system for the dedication of memory storage locations
US6222752
Dynamic word line driver for
cache
US6212616
Even/odd cache directory
mechanism
US6202132
Flexible cache-coherency
mechanism
US6182201
Demand-based issuance of cache
operations to a system bus
US5694573
Shared L2 support for
inclusion property in split L1 data and instruction caches
US5692151
High performance/low cost
access hazard detection in pipelined cache controller using comparators with a
width shorter than and independent of total width of memory address
US5687350
Protocol and system for
performing line-fill address during copy-back operation
US5684976
Method and system for reduced
address tags storage within a directory having a tree-like data structure
US5668972
Method and system for
efficient miss sequence cache line allocation utilizing an allocation control
cell state to enable a selected match line
US5664150
Computer system with a device
for selectively blocking writebacks of data from a writeback cache to memory
US5664147
System and method that
progressively prefetches additional lines to a distributed stream buffer as the
sequentiality of the memory accessing is demonstrated
US5659710
Cache coherency method and
system employing serially encoded snoop responses
US5659699
Method and system for managing
cache memory utilizing multiple hash functions
US5651136
System and method for
increasing cache efficiency through optimized data allocation
US5642491
Method for expanding
addressable memory range in real-mode processing to facilitate loading of large
programs into high memory
US5640534
Method and system for
concurrent access in a data cache array utilizing multiple match line selection
paths
US5640526
Superscaler instruction
pipeline having boundary identification logic for variable length instructions
US5627993
Methods and systems for merging
data during cache checking and write-back cycles for memory reads and writes
US5625793
Automatic cache bypass for
instructions exhibiting poor cache hit ratio
US5625787
Superscalar instruction
pipeline using alignment logic responsive to boundary identification logic for
aligning and appending variable length instructions to instructions stored in
cache
US5623632
System and method for
improving multilevel cache performance in a multiprocessing system
US5615168
Method and apparatus for
synchronized pipeline data access of a memory system
US5613086
Method and system for locking
a page of real storage using a virtual address
US5603011
Selective shadowing and paging
in computer memory systems
US5594876
Arbitration protocol for a
bidirectional bus for handling access requests to a logically divided memory in
a multiprocessor system
US5247647
Detection of deletion of
stored data by concurrently executing processes in a multiprocessing data
processing system
US5228136
Method and apparatus to
maintain cache coherency in a multiprocessor system with each processor's
private cache updating or invalidating its contents based upon set activity
US5220669
Linkage mechanism for program
isolation
Publication Title
US6253372
Determining a communication
schedule between processors
US6247091
Method and system for
communicating interrupts between nodes of a multinode computer system
US6230206
System for internode deadlock
avoidance in parallel database system using as overflow buffer a temporary table
storage allocated to the parallel database application program being executed
US6226695
Information handling system
including non-disruptive command and data movement between storage and one or
more auxiliary processors
US5682491 &n
